Pipelined architecture of a chaotic pseudo-random number generator in a Cyclone V SoC device

In this paper, we present a novel, optimized microarchitecture of a pseudo-random number generator (PRNG) based on the chaotic model with frequency dependent negative resistances (FDNR). The project was focused on optimization of the PRNG architecture to achieve the highest possible output throughput of the generated pseudo-random sequences. As a result we got a model of the pipelined PRNG that was implemented in Cyclone V SoC from Altera and verified experimentally. All versions of the PRNG were tested by standard statistical tests NIST SP800-22. In addition, we also provide a brief comparison with the PRNG implementation in SoC from Xilinx.