Algorithms for packing soft blocks of VLSI systems

This paper contains a review of literature concerning the packing of hard-blocks (of fixed dimensions) and soft-blocks (of fixed area – changeable within specified constraints). These considerations are applicable to the designing of large scale integration chips. In order to solve the problem of packing soft-blocks, three algorithms are introduced and compared: simulated annealing, heuristic constructional algorithm based on five operations to improve packing quality and the algorithm which combines two previous algorithms. Experiments were conducted to compare these algorithms to the best from the literature.