Design optimisation of the deep trench termination for superjunction power devices

Among the numerous solutions developed to improve the voltage handling capability of superjunction power devices, the Deep Trench Termination (DT²) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of TCAD 2D and 3D-simulations allowing the realization of deep trench superjunction devices (diodes and MOS transistors) for 1200 V applications. The work is focused on the influence of the dielectric passivation layer thickness and the field plate length on the breakdown voltage of a DT-SJDiode.